32/64 bits AXI master DMA Core
Details
Category:System on Chip
Created:March 25, 2011
Updated:January 27, 2020
Language:Verilog
Other project properties
WishBone compliant:No
WishBone version:N/A
License:LGPL
Description
罪gle channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control, timeouts and endianess swapping. Based on Provartec PR200http://www.provartec.comipproducts
Related projects
Generic AXI interconnect fabric
http://opencores.orgproject,robust_axi_fabric
