现代IC的设计是一项真正的巨大事业，IC设计工具使工作成为可能。
EDA（电子设计自动化）（也称为ECAD（电子计算机辅助设计））已成为行业的标准。各种软件EDA工具用于设计系统，电路，PCB和组件。但是，在IC设计中，EDA程序的重要性更高。
在本文中，我们将简要介绍Cadence，Synopsys和Mentor图形的一些EDA软件工具。
EDA计划在IC设计中意味着什么？
A common focal point of EDA programs, as they exist today, is to link the various steps involved in smoothly getting from RTL to GDS.
RTL（寄存器传输级别）是根据数字信号流和逻辑操作到单个触发器级别定义的数字电路模型。
GDS stands for graphic database system, and GDSII is the paramount database standard describing IC layout artwork. It is used to contain all the information describing the IC’s layout artwork and can be used for sharing between different tools and for building photomasks.
有多个年代teps along this road, and the key to producing great designs quickly is to integrate the individual steps for flawless hand-off. It is important to note that the various manufacturers handle this critical function in different manners. And, if an issue later in the design cycle calls for a change in an earlier phase, that, too, must be easily applied.
至关重要的是两部分的位置和路线阶段。放置涉及新生IC的亚块的最佳放置，路由是亚块之间的最佳电互连方案的设计。
概要数字工具集
概念’ Digital Toolset is used for silicon chip design, verification, IP integration, and application security testing. Unlike previous generations of EDA, its Fusion Technology eliminates the former hard boundaries between synthesis, place-and-route and signoff, sharing integrated engines across the platform.
融合设计平台。图片来自概念
The Fusion design platform employs machine learning to enable better and faster results by speeding up computation-intensive analyses, predicting outcomes to improve decision-making, and leveraging past learning.
The cloud-based solution is available on Microsoft Azure, Amazon Web Services, and the Synopsys Cloud Solution.
融合设计平台的关键是：
- RTL Synthesis
- 物理实施(RTL-to-GDSII)
- 签收(设计验证)
- Physical Verification(design rules and manufacturability)
- Test Automation
IC Compiler IIis Synopsys’ RTL-to-GDSII tool for place and route, across all types of ICs and process technologies. It spans 16/14nm, 12/10nm, 7/5nm, and sub-5nm geometries.
IC编译器II使设计人员能够按照复杂的布局要求进行快速探索和平面图。IC编译器II可以创建总线结构，处理具有N级物理层次结构的设计，并可以支持乘数实例化块（MIB）。
A design data mismatch inferencing engine analyzes the quality of inputs to deliver design insights even with “incomplete” data early in the design cycle.
Of great importance to designers, Synopsys collaborates closely with all the leading foundries to ensure that IC Compiler II can deliver support for both early prototype design rules and for the final production design rules.
Cadence: Virtuoso and Spectre
Cadence’s IC design tools include Virtuoso and Spectre. Like most of Cadence’s software tools, they are Linux-based and are run on servers. The tightly integrated tools are targeted largely, but not exclusively, at RFICs and RF modules.
Virtuoso
- 电路的示意图
- Layout of circuit
- Design rule check
- Layout vs. schematic
Spectre
- DC，AC和瞬态分析
- 线性电路的S参数分析
- RF analysis for non-linear circuits, including PSS (periodic steady state) and QPSS (quasi-PSS)
Virtuosodesign flow. Image fromCadence
The Virtuoso Layout Suite GXL
TheVirtuosoLayout Suite GXLconsists of automatic layout engines for routing, layout optimization, module generation, and analog/mixed-signal floorplanning. This tool allows an engineer to create various designs (digital, analog, or mixed-signal) and implement them from chip level to device level.
VirtuosoADE Product Suite
TheVirtuosoADE Product Suiteis tightly linked to the Spectre Circuit Simulator as well as to the Virtuoso Suite. This tool is designed for the early stages of the circuit design cycle. Once a circuit block is up and running, it is tested, including its interactions with other blocks in the design.
该套件包括用于设计验证的Virtuoso Ade验证器。此处的目的是确保所有项目设计师合并的所有块以满足所有设计规格。这一至关重要的步骤的旧手动方法是后期问题的重要来源，这些问题会对上市时间产生负面影响。
Spectre Circuit Simulator
The CadenceSpectre Circuit Simulator为模拟，RF和混合信号电路提供香料级模拟。它与Virtuoso自定义设计平台紧密整合在一起，可详细分析到晶体管级别。
该软件包提供了统计分析，以提高IC的生产性和产量，而无需牺牲上市时间。最重要的是，Cadence采用了经过铸造的设备模型，因此在设计过程中会在早期考虑生产性。
SiP Layout
Thesip（包装系统）布局tool provides a constraint-driven and rules-driven substrate layout environment. This includes full 3D design visualization, verification, and editing capabilities.
导师Graphics – Tanner EDA
TheTanner Edaprogram automates the design, layout, and verification of analog/mixed-signal ICs, as well as MEMS. Note that digital IC design is covered by other Mentor tools, such as坦纳数字实施者for the physical design process.
大多数制革商模块既兼容Linux和Windows。
导师的模拟混合信号设计流。图片来自导师.
该产品运营的阶段包括：
- 示意图捕获
- 模拟模拟
- Layout
- Physical verification
坦纳S-Edit捕获示意图
坦纳S-Edit捕获示意图is tightly integrated with simulation. This makes it easy to see results directly on the schematic. Designers can observe the small signal parameter of devices and view model parameters. Waveform cross-probing can be performed to view node voltages and device terminal currents or charges.
Extensive library support serves to maximize the reuse of IP developed in previous projects, or imported from third-party vendors.
制革商T-Spice模拟
For analog simulation,制革商T-Spice模拟呈现通过直流/交流分析，瞬态分析，参数扫描等表征的电路行为。
坦纳波形查看器
Also for analog simulation, the Tanner Waveform Viewer is dynamically linked to Tanner T-Spice simulation and Tanner S-Edit schematic capture.导师notes that该工具可以处理较大的文件（“ 10GB+”）。它会自动计算并显示FFT结果。
坦纳l-edit ic布局
The Tanner L-Edit IC Layout is schematic-driven, imports netlists and automatically generates parameterized cells. DRC (design rule check) displays violations immediately, saving time.
Tanner Calibre One
坦纳（Tanner Caliber One）用于物理验证，并确保布局实际上相当于原理图。检查了与布局有关的效果，以确保它们不会损害设计的性能。该工具可确保最终的生产性。
There are many companies offering EDA tools. We can’t cover them all in this small report, but here is just one more:
Analog Integrated Circuit Design Automation(AIDA) automates the design of analog and mixed-signal ICs. It focuses on efficiently automating repetitive design tasks. It does so partially by facilitating design reuse and by fast response to specification changes of analog cells.
The process of designing an IC is a vast undertaking. The design teams simultaneously working on the project can be located all over the world. The design can incorporate company IP and foundry IP as well as newly developed designs.
Problems can pop up late in the design phase, and for that reason, the most common factor in all IC design software is the tight linking together of all the components. That way, if a problem shows itself in the last stages of verification, it will be easy to change a schematic and to follow all the changes that then occur, and if necessary, compensate for them
