获得高Q XTAL振荡器的收敛性

当模拟高Q晶体振荡器ing Cadence’s Virtuoso Periodic Steady State (PSS) analysis, it is often very difficult to obtain convergence and thus obtain a simulation of phase noise. This is so despite the options specifically available to improve convergence.

In this article, we'll discuss a method that greatly increases the probability of convergence, and achieves this whilst keeping simulations times short. It is a technique that has proven effective in obtaining convergence where the oscillator is embedded in a hierarchy of hundreds of other circuit blocks.

初始设置

It is important to set simulation options that minimize the work of Spectre in finding a solution such that when PSS does converge; it actually converges to an accurate result. There are some default Spectre settings that are unduly restrictive, and for most designs, are simply an accident waiting to happen—for example, “iabstol”. However, for high Q xtal oscillators, the default reltol accuracy is insufficient.

建议的起点是：

• reltol = 10e-6
• iabstol=10p
• Gmin = 10p

Spectre/SPICE defaults are typically 1pA for the current error tolerance and 0.1% for the relative tolerance. SPICE can only converge when variables span a range of no more than about 12 orders of magnitude when using standard double precision arithmetic, so 1pA is very harsh for most circuits. Increasing this value to 100 pA or even 1 nA for large current is sometimes a good idea. However, for reliable accuracy in Phase Noise, the default reltol of 0.1% is nowhere near enough.

A reasonable starting value is 10e-6 but for some circuits this will need to be increased to say, 1e-6. A tell-tale sign of inaccurate results is the presence of step jumps in the phase noise plots.

PSS设置

The PSS form must be set so that a pre trans run “tstab” is always performed. Extensive simulations have shown that, for difficult convergence oscillators, that the options designed to improve convergence, essentially, always fail. That is the detect “steady state” and “calculate initial conditions” should never be engaged.

建议的起点是：

• Number of Harmonics=50
• Accuracy Defaults=Conservative
• Run Transient=YES
• 停止时间=下面描述
• Detect Steady=Not enabled
• 计算初始条件=未启用

除简单的正弦波输出外，拍摄方法通常是任何振荡器系统的最佳方法。大多数振荡器应用都需要一个平方限制器，以使系统高度非线性。因此，默认值50谐波是一个很好的起点。对于特殊的困难电路，很可能需要100谐波。同样，如果总相位噪声图不光滑，则表明该图很可能是错误的。保守的精度设置信号幽灵实际上使最初的10E-6设置进行了retol，甚至更紧。

Note that, as usual, set the oscillator nodes to the XTAL nodes.

PNoise Setup

The PNoise setup is relatively standard. For accuracy, set the default maximum sidebands to 50.

为了减少模拟时间，但仍然获得合理的平滑情节，每十年10分的对数图就足够了。通常，关注的是相位噪声，因此请选中适当的框。

输出/绘图设置

To ensure that the oscillator actually works, a Cadence Stability Analysis should be run first.

不幸的是，在撰写本文时，Cadence稳定性分析具有一个基本缺陷，可防止循环增益边距和循环相位边缘使用其直接图特征输出。（这是er .. ahhmmm…尽管门票被提交给他们的Ahmmm…支持部门…）

The Cadence Spectre log will produce the following…

“警告（Spectre-16922）：由于电路是一个正反馈系统并且不稳定，因此无法获得相位边距并获得边距。这是因为当环形阶段交叉零度时，环状的大小大于10.003 MHz的大小。为了使电路保持稳定，请确保在环形阶段越过零度时，环状的大小小于一个。”

所以，当然，这是一个振荡器！只是吐出结果DAH！…

因此，……输出表格应使用手动脚本设置，如下所示：

Loop Phase

phasedegunwrapped（getData（“ loopgain”？result“ stb”））

Loop Gain

db（mag（getData（“ loopgain”？result“ stb”）））））））

Oscilation Frequency

cross(leafValue(phaseDegUnwrapped(getData("loopGain" ?result "stb"))) "0" 1 "either" nil nil nil)

Oscilation Gain

值（叶值（db（mag（getData（“ loopgain”？result'stb”）））））cross（叶价值（phasedeGunwrapped（getData（“ loopgain”？loopgain''？结果“ stb”））“ 0” 0“” 1“零））

Sometimes, depending on the circuit, the phase is shifted in lumps of 360 degs, so the crossing point “0” should be modified appropriately.

XTAL Model Setup

The schematic for the XTAL should be set up such that the schematic calculates the required XTAL inductance from the c1 of the XTAL and the XTAL frequency.

Thus the inductor should have the following set in its inductance field of its setup form:

1/(pPar("C1")*((2*3.141592654*pPar("FS"))*(2*3.141592654*pPar("FS"))))

组件iClamp是一个Verilog电压/电流限制器，有助于收敛，因为高Q XTAL可以生成100kV类型的数字，因此在收敛过程中，Spice可以产生更高的电压。它有助于避免那些“最后的收敛节点= 123.8 mV”错误。但是，可能不是必需的。

它的代码是：

`include "constants.vams"

`include "disciplines.vams"

模块vclamp_verilog（a，b）;

inot a;

electrical A;

inout B;

electrical B;

parameter real imax = 0.5 ;

parameter real vmax = 1 ;

parameter real i0 = 1E-18;

模拟开始

我(A, B) < + imax *双曲正切(i0 * sinh(100 *双曲正切((40 / vmax / 100) *V(A,B))));

end

The capacitor across the inductor is a dummy capacitor of very small value, typically 1e-20F. It is required as a convenient method to force the initial voltage across the inductor to 0V. This node voltage setting is part of this convergence technique.

收敛法

高Q Xtal的收敛性问题在于，幽灵仅因为Q很高而难以收敛。对于同一电路，但Q较低，通常没有问题。因此，该方法是为低Q电路求解，并使用该方法在完整Q处有助于解决溶液。

The key principle is that a low Q XTAL will reach its steady state value much quicker than a high Q XTAL. That is, if the XTAL is “De-Qed” by a factor of 100, then the simulation will be 100 times quicker to settle.

The Q of an XTAL oscillator is determined by the C1 (series resistance) of the XTAL. However, the steady state current in the inductor of the XTAL is independent of C1. Thus the low-Q inductor current may be used as the initial current for the full Q XTAL.

So, the principle of the method is to initialize the inductor current with a current close to what it would be in steady state, with that current determined by first running a low Q version of the circuit.

设置仿真的一种方便方法是引入一个乘以C1的变量（例如，QR），以便首先设置QR，为100，对于低Q运行，然后将整个Q运行设置为1。例如：

Example Schematic

Example Waveforms

顶部图显示了低Q和高Q运行的X1处信号电压。底部图显示了低Q和高Q运行的电感电流。

可以看出，从低q配置确定的值，可以立即启动高Q配置。

This allows PSS a much better starting condition so that it is more likely to converge. In this particular case, the PSS tstab time was only set to 1us. For difficult cases, it will need to be determined empirically.

特兰

PSSR

Phase Noise

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